Modern integrated circuits such as a system on a chip (SOC) may include hundreds if not thousands of embedded memories such as static random access memories (SRAMs). The bit cells in the embedded SRAMs make up the smallest features in the SOC and so they are the most vulnerable to manufacturing errors. Because of the small size of the SRAM bitcells, manufacturing defects will affect the SRAM bit cells before affecting larger features such as logic gates. Depending upon the process node and the number of the SRAM bit cells, the SOC may be required by foundry rules to implement column redundancy and/or row redundancy. For example, 90% of the total SRAM bitcells on an SOC may need to be replaceable through redundancy schemes.
In the absence of any manufacturing defects, a memory with redundant columns and/or redundant rows operates without using these redundant features. But if a manufacturing defect causes an error, the function of the defective column or row is replaced by its redundant counterpart. To effect this replacement, a redundancy scheme requires some way to identify the defective feature (column or row). Moreover, an integrated circuit such as a system on a chip (SOC) may include assorted embedded memories. So the redundancy scheme for an SOC must not only identify the defective feature but also the particular memory having the defective feature. For example, suppose there are two thousand embedded SRAMs each having one hundred and twenty eight columns. Identifying a defective column from 128 possibilities for each of the two-thousand SRAMs requires two-thousand 7-bit words (14,000 bits total). It is conventional to use a fuse-based ROM to store the redundancy information. But if the redundancy information is tens of thousands of bits, storing this information in a fused-based ROM then demands substantial die space to instantiate so many fuses.
Accordingly, there is a need in the art for a more efficient enabling of redundancy in memory arrays.